Finite element modelling and experimental characterisation of paralleled SiC MOSFET failure under avalanche mode conduction (2015)

First Author: Hu J
Attributed to:  Underpinning Power Electronics 2012: Devices Theme funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/epe.2015.7309180

Publication URI: http://dx.doi.org/10.1109/epe.2015.7309180

Type: Conference/Paper/Proceeding/Abstract