A reconfigurable cache architecture for energy efficiency (2011)

First Author: Sundararajan K
Attributed to:  Automated Synthesis of High Performance Low Power Embedded Systems funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1145/2016604.2016616

Publication URI: http://dx.doi.org/10.1145/2016604.2016616

Type: Conference/Paper/Proceeding/Abstract

ISBN: 9781450306980