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High Speed CPU Simulation Using LTU Dynamic Binary Translation

First Author: Jones D

Attributed to: Automated Synthesis of High Performance Low Power Embedded Systems funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1007/978-3-540-92990-1_6

Publication URI: http://dx.doi.org/10.1007/978-3-540-92990-1_6

Type: Book Chapter

Book Title: High Performance Embedded Architectures and Compilers (2009)

Page Reference: 50-64

ISBN: 978-3-540-92989-5