Eliminating Synchronization Latency Using Sequenced Latching (2014)
Attributed to:
Reliable cell design methods for variable processes (RelCel)
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2013.2243177
Publication URI: http://dx.doi.org/10.1109/tvlsi.2013.2243177
Type: Journal Article/Review
Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue: 2