Sequence-Aware Watermark Design for Soft IP Embedded Processors (2016)
Attributed to:
Resilient and Testable Energy-Efficient Digital Hardware
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2015.2399457
Publication URI: http://dx.doi.org/10.1109/tvlsi.2015.2399457
Type: Journal Article/Review
Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue: 1