Central-Tapped Node Linked Modular Fault-Tolerance Topology for SRM Applications (2016)

First Author: Hu Y
Attributed to:  High-temperature Silicon Carbide Electronics (HITSIC) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tpel.2015.2414664

Publication URI: http://dx.doi.org/10.1109/tpel.2015.2414664

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Power Electronics

Issue: 2