An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors (2015)
Attributed to:
Multiprocessors: From Microarchitecture to Semantic Theory
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1145/2830772.2830775
Publication URI: http://dx.doi.org/10.1145/2830772.2830775
Type: Conference/Paper/Proceeding/Abstract
ISBN: 9781450340342