A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF<inline-formula> <tex-math notation="LaTeX">$(2^{m})$ </tex-math></inline-formula> (2015)

First Author: Poolakkaparambil M
Attributed to:  Process Variation Aware Synthesis of Nano-CMOS Circuits funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2014.2341631

Publication URI: http://dx.doi.org/10.1109/tvlsi.2014.2341631

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue: 8