A hybrid reliability assessment method and its support of sequential logic modelling (2014)

First Author: Pagliarini S
Attributed to:  Process Variation Aware Synthesis of Nano-CMOS Circuits funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/iolts.2014.6873690

Publication URI: http://dx.doi.org/10.1109/iolts.2014.6873690

Type: Conference/Paper/Proceeding/Abstract