A placement strategy for reducing the effects of multiple faults in digital circuits (2014)

First Author: Pagliarini S
Attributed to:  Process Variation Aware Synthesis of Nano-CMOS Circuits funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/iolts.2014.6873674

Publication URI: http://dx.doi.org/10.1109/iolts.2014.6873674

Type: Conference/Paper/Proceeding/Abstract