Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM (2012)

First Author: Mohanty S
Attributed to:  Process Variation Aware Synthesis of Nano-CMOS Circuits funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1016/j.vlsi.2011.07.001

Publication URI: http://dx.doi.org/10.1016/j.vlsi.2011.07.001

Type: Journal Article/Review

Parent Publication: Integration

Issue: 1