📣 Help Shape the Future of UKRI's Gateway to Research (GtR)

We're improving UKRI's Gateway to Research and are seeking your input! If you would be interested in being interviewed about the improvements we're making and to have your say about how we can make GtR more user-friendly, impactful, and effective for the Research and Innovation community, please email gateway@ukri.org.

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization (2011)

First Author: Banerjee S

Attributed to: Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1166/jolpe.2011.1160

Publication URI: http://dx.doi.org/10.1166/jolpe.2011.1160

Type: Journal Article/Review

Parent Publication: Journal of Low Power Electronics

Issue: 4