A Routing-Aware ILS Design Technique (2011)

First Author: Banerjee S
Attributed to:  Process Variation Aware Synthesis of Nano-CMOS Circuits funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2010.2078526

Publication URI: http://dx.doi.org/10.1109/tvlsi.2010.2078526

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue: 12