Improving the Tolerance of Stochastic LDPC Decoders to Overclocking-Induced Timing Errors: A Tutorial and a Design Example (2016)
Attributed to:
Highly-parallel algorithms and architectures for high-throughput wireless receivers
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/access.2016.2550179
Publication URI: http://dx.doi.org/10.1109/access.2016.2550179
Type: Journal Article/Review
Parent Publication: IEEE Access