Formal verification of clock domain crossing using gate-level models of metastable flip-flops (2016)
Attributed to:
Globally Asynchronous Elastic Logic Synthesis (GAELS)
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Publication URI: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7459466&isnumber=7459269
Type: Conference/Paper/Proceeding/Abstract