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Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path (2016)

First Author: Benafa O

Attributed to: A4A: Asynchronous design for analogue electronics funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/newcas.2016.7604821

Publication URI: http://dx.doi.org/10.1109/newcas.2016.7604821

Type: Conference/Paper/Proceeding/Abstract