📣 Help Shape the Future of UKRI's Gateway to Research (GtR)

We're improving UKRI's Gateway to Research and are seeking your input! If you would be interested in being interviewed about the improvements we're making and to have your say about how we can make GtR more user-friendly, impactful, and effective for the Research and Innovation community, please email gateway@ukri.org.

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications (2016)

First Author: Li A

Attributed to: Channel Decoder Architectures for Energy-Constrained Wireless Communication Systems: Holistic Approach funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/access.2016.2599408

Publication URI: http://dx.doi.org/10.1109/access.2016.2599408

Type: Journal Article/Review

Parent Publication: IEEE Access