An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network (2016)
Attributed to:
Self-repairing Hardware Paradigms based on Astrocyte-neuron Models
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/ssci.2016.7850175
Publication URI: http://dx.doi.org/10.1109/ssci.2016.7850175
Type: Conference/Paper/Proceeding/Abstract