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A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs

First Author: Stewart R

Attributed to: Programmable embedded platforms for remote and compute intensive image processing applications funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1007/978-3-319-49956-7_14

Publication URI: http://www.macs.hw.ac.uk/~rs46/papers/dlmcs2016/RIPL-dlmcs2016.pdf

Type: Book Chapter

Book Title: Algorithms and Architectures for Parallel Processing (2016)

Page Reference: 174-188