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Ultimate Scaling Limit of Nanoscale Devices: Graphene Nano-gaps (Poster) (2016)

First Author: Syed Ghazi Sarwat

Attributed to: Designing Nanosystems: the CMOS Way funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Publication URI: https://mme.iitm.ac.in/?p=723

Type: Other