Improved Reliability of FPGA-Based PUF Identification Generator Design (2017)
Attributed to:
CSIT 2
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1145/3053681
Publication URI: http://dx.doi.org/10.1145/3053681
Type: Journal Article/Review
Parent Publication: ACM Transactions on Reconfigurable Technology and Systems
Issue: 3