Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip (2017)

First Author: Zhang G
Attributed to:  Globally Asynchronous Elastic Logic Synthesis (GAELS) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2017.2729081

Publication URI: http://dx.doi.org/10.1109/tvlsi.2017.2729081

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue: 11