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On Microarchitectural Mechanisms for Cache Wearout Reduction (2017)

First Author: Valero A

Attributed to: M3: Managing Many-Cores for the Masses funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2016.2625809

Publication URI: http://dx.doi.org/10.1109/tvlsi.2016.2625809

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue: 3