A Data-Driven Verilog-A ReRAM Model (2018)
Attributed to:
Reliably unreliable nanotechnologies
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tcad.2018.2791468
Publication URI: http://dx.doi.org/10.1109/tcad.2018.2791468
Type: Journal Article/Review
Parent Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue: 12