A Data-Driven Verilog-A ReRAM Model (2018)

First Author: Messaris I

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/TCAD.2018.2791468

Publication URI: http://dx.doi.org/10.1109/TCAD.2018.2791468

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue: 12