Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms (2017)
Attributed to:
SERT: Scale-free, Energy-aware, Resilient and Transparent Adaptation of CSE Applications to Mega-core Systems
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/iolts.2017.8046197
Publication URI: http://dx.doi.org/10.1109/iolts.2017.8046197
Type: Conference/Paper/Proceeding/Abstract