A compact 14-bit 110 KS/s two-stage incremental S? ADC for CMOS image sensors (2017)

First Author: Giorgio F

Attributed to: Designing Nanosystems: the CMOS Way funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/mwscas.2017.8053139

Publication URI: http://dx.doi.org/10.1109/mwscas.2017.8053139

Type: Conference/Paper/Proceeding/Abstract