Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis (2019)
Attributed to:
PRiME: Power-efficient, Reliable, Many-core Embedded systems
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tcad.2018.2821563
Publication URI: http://dx.doi.org/10.1109/tcad.2018.2821563
Type: Journal Article/Review
Parent Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue: 4