Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations (2018)
Attributed to:
Channel Decoder Architectures for Energy-Constrained Wireless Communication Systems: Holistic Approach
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tcsii.2018.2807362
Publication URI: http://dx.doi.org/10.1109/tcsii.2018.2807362
Type: Journal Article/Review
Parent Publication: IEEE Transactions on Circuits and Systems II: Express Briefs
Issue: 12