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Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis (2019)

First Author: Murray K

Attributed to: PRiME: Power-efficient, Reliable, Many-core Embedded systems funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tcad.2018.2821563

Publication URI: http://cas.ee.ic.ac.uk/people/gac1/pubs/KevinTCAD18.pdf

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue: 4