Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization (2019)

First Author: Bhardwaj K

Attributed to: Bayesian Optimization methods funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/lca.2019.2910521

Publication URI: http://dx.doi.org/10.1109/lca.2019.2910521

Type: Journal Article/Review

Parent Publication: IEEE Computer Architecture Letters

Issue: 2