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Spatial Sensitivity of Silicon GAA Nanowire FETs Under Line Edge Roughness Variations (2018)

First Author: Indalecio G

Attributed to: Modelling of Carrier Transport in Ultra Thin Body Transistors funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/jeds.2018.2828504

Publication URI: http://dx.doi.org/10.1109/jeds.2018.2828504

Type: Journal Article/Review

Parent Publication: IEEE Journal of the Electron Devices Society