Mapping Large LSTMs to FPGAs with Weight Reuse (2020)
Attributed to:
Event-based parallel computing - partially ordered event-triggered systems (POETS)
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1007/s11265-020-01549-8
Publication URI: http://dx.doi.org/10.1007/s11265-020-01549-8
Type: Journal Article/Review
Parent Publication: Journal of Signal Processing Systems
Issue: 9