Verifying parallel dataflow transformations with model checking and its application to FPGAs (2019)

First Author: Stewart R
Attributed to:  Border Patrol: Improving Smart Device Security through Type-Aware Systems Design funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1016/j.sysarc.2019.101657

Publication URI: http://dx.doi.org/10.1016/j.sysarc.2019.101657

Type: Journal Article/Review

Parent Publication: Journal of Systems Architecture