Capacitor Voltage Balancing Algorithm with Redundant Level Modulation for a Five Level Converter with Reduced Device Count (2020)
Attributed to:
Converter Architectures
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/ipemc-ecceasia48364.2020.9367875
Publication URI: http://dx.doi.org/10.1109/ipemc-ecceasia48364.2020.9367875
Type: Conference/Paper/Proceeding/Abstract