A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis (2022)
Attributed to:
PRiME: Power-efficient, Reliable, Many-core Embedded systems
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tcad.2021.3075651
Publication URI: http://dx.doi.org/10.1109/tcad.2021.3075651
Type: Journal Article/Review
Parent Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue: 4