High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point. (2023)
Attributed to:
Application Customisation: Enhancing Design Quality and Developer Productivity
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tnnls.2021.3116302
PubMed Identifier: 34644253
Publication URI: http://europepmc.org/abstract/MED/34644253
Type: Journal Article/Review
Volume: 34
Parent Publication: IEEE transactions on neural networks and learning systems
Issue: 8
ISSN: 2162-237X