Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning (2023)

First Author: Tompazi S
Attributed to:  Centre for Secure Information Technologies (CSIT) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/mdat.2021.3135318

Publication URI: http://dx.doi.org/10.1109/mdat.2021.3135318

Type: Journal Article/Review

Parent Publication: IEEE Design & Test

Issue: 1