Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns (2022)

First Author: Szafarczyk R
Attributed to:  Exploiting Parallelism through Type Transformations for Hybrid Manycore Systems funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/fpl57034.2022.00033

Publication URI: https://api.elsevier.com/content/abstract/scopus_id/85149328874

Type: Conference/Paper/Proceeding/Abstract