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Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications (2017)

First Author: Al-Ameri T

Attributed to: Quantum Electronics Device Modelling (QUANTDEVMOD) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/jeds.2017.2752465

Publication URI: http://dx.doi.org/10.1109/jeds.2017.2752465

Type: Journal Article/Review

Parent Publication: IEEE Journal of the Electron Devices Society

Issue: 6