Synthesis of Processor Instruction Sets from High-Level ISA Specifications (2014)
Attributed to:
Globally Asynchronous Elastic Logic Synthesis (GAELS)
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tc.2013.37
Publication URI: http://dx.doi.org/10.1109/tc.2013.37
Type: Journal Article/Review
Parent Publication: IEEE Transactions on Computers
Issue: 6