Maximising Parallel Memory Access for Low Latency FPGA Designs (2022)
Attributed to:
Event-based parallel computing - partially ordered event-triggered systems (POETS)
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/iscas48785.2022.9937955
Publication URI: http://dx.doi.org/10.1109/iscas48785.2022.9937955
Type: Conference/Paper/Proceeding/Abstract