Engineering of Grain Boundaries in CeO 2 Enabling Tailorable Resistive Switching Properties (2023)
Attributed to:
ECCS - EPSRC Development of uniform, low power, high density resistive memory by vertical interface and defect design
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1002/aelm.202201186
Publication URI: http://dx.doi.org/10.1002/aelm.202201186
Type: Journal Article/Review
Parent Publication: Advanced Electronic Materials
Issue: 5