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10kV+ Rated SiC n-IGBTs: Novel Collector-Side Design Approach Breaking the Trade-Off between dV/dt and Device Efficiency (2023)

First Author: Almpanis I

Attributed to: Underpinning Power Electronics switch optimisation Theme funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.4028/p-21h5lt

Publication URI: https://api.elsevier.com/content/abstract/scopus_id/85166233560

Type: Journal Article/Review

Parent Publication: Key Engineering Materials