Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation
Attributed to:
Event-based parallel computing - partially ordered event-triggered systems (POETS)
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1007/978-3-319-56258-2_15
Publication URI: http://dx.doi.org/10.1007/978-3-319-56258-2_15
Type: Book Chapter
Book Title: Applied Reconfigurable Computing (2017)
Page Reference: 168-176
ISSN: 16113349 03029743