Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions (2021)
Attributed to:
PRiME: Power-efficient, Reliable, Many-core Embedded systems
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/fpl53798.2021.00082
Publication URI: http://dx.doi.org/10.1109/fpl53798.2021.00082
Type: Conference/Paper/Proceeding/Abstract