KaratSaber: New Speed Records for Saber Polynomial Multiplication using Efficient Karatsuba FPGA Architecture (2023)

First Author: Wong Z
Attributed to:  Centre for Secure Information Technologies (CSIT) - Phase 3 funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tc.2023.3238129

Publication URI: http://dx.doi.org/10.1109/tc.2023.3238129

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Computers