Engineering of Grain Boundaries in CeO2 Enabling Tailorable Resistive Switching Properties (2023)
Attributed to:
ECCS - EPSRC Development of uniform, low power, high density resistive memory by vertical interface and defect design
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.17863/cam.94727
Publication URI: https://www.repository.cam.ac.uk/handle/1810/347312
Type: Journal Article/Review