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The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units (2008)

First Author: Yu C

Attributed to: Reconfigurable Architectures for Floating Point Applications funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/spl.2008.4547733

Publication URI: http://dx.doi.org/10.1109/spl.2008.4547733

Type: Conference/Paper/Proceeding/Abstract