📣 Help Shape the Future of UKRI's Gateway to Research (GtR)

We're improving UKRI's Gateway to Research and are seeking your input! If you would be interested in being interviewed about the improvements we're making and to have your say about how we can make GtR more user-friendly, impactful, and effective for the Research and Innovation community, please email gateway@ukri.org.

The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures (2013)

First Author: Thomas D

Attributed to: Optimising Hardware Acceleration for Financial Computation funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2012.2194171

Publication URI: http://dx.doi.org/10.1109/tvlsi.2012.2194171

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue: 4